Having some PCB experience, I disagree. Targeting higher specs like PCIe 5.0 usually requires more expensive PCB materials and tighter qualifications at the test stage.
If the boards were only being tested to PCIe 4.0 (their official spec) then you can't guarantee they perform the same as SKUs targeting PCIe 5.0.
You can't notice these differences with your eyes.
The general advice is 5 mils Intra-Pair and no specific requirement for Inter-Pair. These follow the same engineering guidelines as PCIe 4.0, with identical impedance and coupling. As far as I can tell, there are no significant differences, aside from PCIe 5.0 having smaller theoretical margins. Even then, the 5 mils spec is likely overkill for both.
From what I’ve read, a well-designed PCB that supports PCIe 4.0 should also meet PCIe 5.0 requirements electrically and for signaling. I suspect the issue may be related more to power delivery or EMC than to trace layout or stack-up. Alternatively, it could just be an AMD policy decision to limit PCIe 5.0 support on this chipset variant, rather than a design flaw.
I'm not sure a PCB of such size can be made (without making the PCB actually more expensive) partially with worse and better materials, since the board does support four PCIe 5.0 lanes. The question is how much cheaper would it be to route the 16 lanes only for 4.0 speed rating.
If the boards were only being tested to PCIe 4.0 (their official spec) then you can't guarantee they perform the same as SKUs targeting PCIe 5.0.
You can't notice these differences with your eyes.