Cycle-accurate software emulation is a topic that I've been looking into on and off for years.
The Higan concurrency architecture hit a wall because it needs to sync between modules every single cycle, what gets very expensive as the clock rates go up.
But you don't need to sync every single cycle, especially once CPUs started getting caches, so we just need a new concurrency architecture that's flexible enough to only sync when needed.
I've been experimenting with an actor based concurrency model which seems to be fast enough for a cycle-accurate N64 emulator (though I won't know until I have the RSP and RDP implemented). I'm hoping it might even be fast enough for 6th gen consoles, perhaps when combined with other techniques like a cycle-accurate jit and fine-grained memory locks.
I'll have to post an article if it ever gets to a workable state.
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As for cycle-accurate FPGA emulators, I don't think they are cost-effective even for something like the N64, yet alone a 360. You can get 90% of the way there with a cycle accurate CPU, shared bus, cycle accurate RSP/RDP. But you have to map the RDRAM onto DDR3 memory and the timings don't really line up. The linked UltraFP64 project doesn't even try for accurate RAM timings and will preform better than a real N64. I suspect the WIP n64 core for MiSTer is much the same.
You could build a custom board with memory that actually matches the timings, but that gets expensive.
The Higan concurrency architecture hit a wall because it needs to sync between modules every single cycle, what gets very expensive as the clock rates go up.
But you don't need to sync every single cycle, especially once CPUs started getting caches, so we just need a new concurrency architecture that's flexible enough to only sync when needed.
I've been experimenting with an actor based concurrency model which seems to be fast enough for a cycle-accurate N64 emulator (though I won't know until I have the RSP and RDP implemented). I'm hoping it might even be fast enough for 6th gen consoles, perhaps when combined with other techniques like a cycle-accurate jit and fine-grained memory locks.
I'll have to post an article if it ever gets to a workable state.
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As for cycle-accurate FPGA emulators, I don't think they are cost-effective even for something like the N64, yet alone a 360. You can get 90% of the way there with a cycle accurate CPU, shared bus, cycle accurate RSP/RDP. But you have to map the RDRAM onto DDR3 memory and the timings don't really line up. The linked UltraFP64 project doesn't even try for accurate RAM timings and will preform better than a real N64. I suspect the WIP n64 core for MiSTer is much the same.
You could build a custom board with memory that actually matches the timings, but that gets expensive.