From working in a somewhat related discipline, the PDKs for the high end nodes (think tsmc N16 and lower) are quite hard to obtain and require your org to pass security audit. In addition to that the cadence licenses are priced very much for a big-org rather than a startup.

Does your chip absolutely need a modern node? I'm assuming you've seen the open source skywater pdk, but here it is just in case. https://github.com/google/skywater-pdk

Thanks. Do you have info about requirements of the security audit and other prerequisites to get the PDKs?

You don't need to make real chip to estimate performance. You just need to make logic model and run it on software FPGA simulator and this will be enough for business plan.

So forget nm, just run your idea on simulator, or on big FPGA.

Second, in modern world, hardware is only fraction of all costs. The largest part is product package and distribution, plus marketing. Marketing of high tech could easy cost 10x hardware, even 20x is not limit.

If separate only production, largest part is software development/support pipeline (2x-5x).

Even if you will achieve zero hardware cost, and some way avoid distribution/marketing, there still will be huge expenses on software development/support.

Third, even when you will achieve ready product in quantities, you will need to wait few years, so people, will see your product give them advantages (that's why software is 5x hardware).

And you are wrong, if think, you could fool investors and jump over some of steps above.

As conclusion, focus on create sustainable design/production pipeline, don't focus on low hardware costs.

If you will achieve (and show) sustainable design/production pipeline for abstract digital chip, you will got money without chip idea.

Logic model is not enough. One needs to know the process PDK to estimate performance / power consumption / cost of the chip.

What do you mean by "design/production pipeline"?

Many people think of product, as achieve Supernova explosion and then just duplicate and sell.

In reality, product is lot of Supernova explosions.

1. You make one explosion (yes, its really hard), and deliver results to consumer.

2. You work hard to got ANY breadcrumbs of feedback.

3. You become Buddha of your product, trying to got some enlightenment from feedback.

4. You gather all your thoughts, and return to 1.

To make good hardware, you must repeat this steps at least 5 times. But if you have no previous experience, you will 3-5 times make dumb tries, before achieve good repeatability.

All semiconductors industry life is just constant repeat-repeat-repeat, sometimes make small advancement.

I see misunderstanding.

Do you play games? Do you know strategies, like HMM or Starcraft?

I played HoMM but failed to understand how to play well.

Ok. You know, exists different maps. One type of maps called many islands. On island map many things possible to do only on terrain (island), and some things just impossible to do on water.

In semiconductors, mono-crystal is like islands - it have perfect parts, and have defects, where 10nm will not work at all.

People spent lot of time to figure out, what to do with defects, but complete solution for all cases does not exist.

Most know solutions, to make modular structure, so parts appear under defects will just disabled by seals (cut by laser).

For example, Intel large die could be with 8 cores, but 2-4 will be disabled after testing, and than will marketed 3 types of CPUs - 4,6 cores (they don't like odd numbers, but I know well, marketed 3-cores CPUs). Other solution, to make few Cache parts considering some disable.

RAM/Flash chips nearly all now typically made modular, so they have for example 6 parts in design, but marketed chip will have 2-4 working parts.

Latest idea, most successfully used by AMD, to use chiplets - they use two (or more) technologies.

From first view could consider chiplet as one core or even one part of chip - Cache or HBM or even Flash.

As interposer (base) used something like old 45nm (more tolerate for defects) and on it placed one or more 10nm or better chiplets, connected with TSVs (Throw-Silicon-Via). Chiplets could be placed side-by-side or one on other (I hear about 8-level chips, but sure, for heat consideration in AMD CPU/APU used 2-level design).

Interposer could be passive (just pads/wires) or active (some silicone elements or even logic/analog modules).

Also exists just classical interposer printed boards, but they are very limited.

What I want say, performance of your chip will depend, on how well it suited for anti-defects tricks, such as modular design and/or chiplets design.

Unfortunately, silicon interposer technology is very young and not mature, just few months ago appear first industry standard, and just now conducted r&d on Open Source interposer tech.

So there are not much to read, but silicon interposer will affect all new designs in very dramatic way.

As for me, most revolutionary example, joint venture design, Intel CPU with AMD chiplet GPU (Core i7-8809G with Radeon RX Vega M GH graphics ).

Thank you. The game analogy is weird, but okay. I already know the basic bits about defects, but not all details you mentioned.

You are welcome. Ask questions, I'm sure you have, and I could answer many (sure not all).

Main question I have that is not minor is how to get funding after I have simulations that show my design's merit. I have no such experience at all.

This is impossible to answer, because investors thinking totally other way.

Investor want to see MARKET fit. They are reasonable people, but best you can do, give them formula with good foundations, like: "if on January 10, you invest x1 amount of cash, in x2 days will receive product, which x3 number of people will buy for x4 dollars, before end of year".

For example, for Arduino-like products, number of potential customers is just about few millions persons, and it have relatively low barriers for new producers.

Because of these characteristics of Arduino-like market, there near impossible to make profitable full scale semiconductor business, as you will need to fight your niche vs many other producers.

So ALL Arduino businesses, really use "two-legs" business model, or "many legs", where Arduino product is just one income source and exists one or more other powerful income sources.

Other example, Amazon Ring. From first view, they are just digital camera business for very specific niche, not very sophisticated technically. But to defend their market from other producers, they registered somewhere about 80 patents, which tightly cover their niche and some nearest neighbors.

Really exists many variants of limitations, which could defend your market from other producers, but this is too broad talk, to speak from what you already tell.

So, what I still trying to say - you going wrong way, you need to talk with investors on business language, not technical language.

Other important thing, nearly all engineers don't understand - good enough service (availability) is more important than design performance.

What I mean, imagine, two people created computers. First, created 0.5MIPS, but with excellent service, so people got ready money machine for business, near without outages, lets state something like 99% availability (maximum 14 hours offline per month), which you could just buy when want. Second created 5MIPS (magnitude faster), but cannot produce in quantities, with any problem people must wait 2 weeks or more to got service.

Even if second producer marketing his computer with same price as first, but in reality you cannot buy/use it, this means, that second producer will lost his opportunity.

This is oversimplified example. In real life appear lot of cases, like Pentium 4, which was technically nightmare, but Intel survive, because have products portfolio, in which P4 was total loss, but others keep company afloat, and because, at the time of P4, from other large CPU vendors, only survived AMD, which was incapable to fill up market, even when Intel fail, so people buy bad P4.

Investor want you to prove, that your product will be not just simulation, but that you could someway keep afloat, even in case of huge failure.

Second important thing, that you must be ready to scale, if market will grow above expectations.

And with semiconductors, this is near impossible in 10nm business, because all Fabs have their own custom solutions to achieve this.

Only Intel is legendary, rumors said, they could just copy design to ANY their Fab (not exact, but near to truth, unfortunately also have limitations), and scale near any product on demand. All other manufacturers have extreme troubles when need to "just copy" product to other Fab, they spending months to do this "just copy".

I'm pretty sure if you can figure out how to arrange the many millions of dollars of funding and hire the various domain experts required to get a cutting-edge (or even last-gen) chip off the ground, your questions would get answered automatically.

Which is not to say they're not interesting questions, but the answers will not be actionable information without the aforementioned money and people.

It's a bit like a single carpenter asking about how you get a permit to build a skyscraper.

I need to measure my preliminary design before the moment I ask for money. If I don't, there will be simply no reason to give me the money.

To me, it sounds you are going to need money to measure your preliminary design. Investors appreciate taking a methodological approach to raising rounds of money for de-risking, rather than "I need $50mm upfront to do everything."

I manage products on the board level, never been down to chip design. Are there design agencies/firms who are familiar with the processes (but are not fabs) that can be engaged to help de-risk your design / assess the manufacture-ability of your chip?

I think that the level of expression of my design that will be necessary to pass it to such design agency under the condition of absence of concrete PDKs is so abstract that it will probably be pointless to do this - at this level my design has almost no information and I really don't see that it's wise to make blind preliminary decisions, and I don't want to outsource the work that I could do myself and hold myself accountable. At least I want to make the more concrete (intermediate) design myself from scratch and only then pass it on to experts to elaborate and improve it.

Fair enough.

You could interpret your original post that the customer-side of things is a foregone conclusion (as in you've talked to a lot of prospective customers and you have high confidence your product will sell), now you just need to focus on designing the product. Is that the case?

If you've talked to customers and have high confidence, why not raise money on the basis of a compelling product?

My idea is a new architecture for general-purpose processors / FPGAs. It may turn out a new successful processor architecture, or just a new FPGA / FPGA-like architecture, or it may be a practically unviable, unsuccessful idea. Need to make actual simulations to see if it is competitive or not. So in the case that the architecture is good, there is no doubt that the product will be in demand. The main question is whether my idea will actually work (architecture is competitive).

No offense intended, but either you don't have a firm conception of just what FPGAs/ASICs are, or this is actually truly revolutionary. Built it in a simulator and see what the performance numbers are. Even talking to TSMC/Intel/Samsung is a post-funding thing, which your shouldn't have any problem raising if it actually works (Hell, DM me if you actually prove it, I'd go in).

My problem is I don't know how to simulate without concrete PDK data and get useful numbers. My prototype design will be lost, unguided.

DM to where?

Lol, fair point, username at gmail

Why do think your architecture needs pdk information? You should be able to show a _massive_ improvement at the logic gate level, then get funding to hire a security team which would let you pass the fabs audits

Gate-level model is meaningless for measuring performance without parameters outside of the model.

If I make only a gate-level model, I have no idea how to prove the benefit of my design, short of just showing it in entirety.

General purpose processors and FPGAs are entirely different and share very few components or architectural characteristics.

Setting that aside, if you have some revolutionary design for an architecture, that should already be abundantly clear from emulating your designs on FPGA. If you aren’t completely sure (and have evidence to prove) that your design is significantly better than anything that has been made before, you’re not at the stage where you should be thinking about manufacturing a chip with modern hardware. As was said elsewhere, making a chip is a phenomenally capital intense process so if you’re planning on competing with any existing hardware you’re going to need to justify that investment with radical gains, not incremental improvements. If you have an idea which you think could speed up existing hardware, your best bet is to work with/sell IP to companies which already design that hardware since it’s just not worth the investment needed to start a whole new chip company for a potentially 10% better CPU/FPGA.

I just can't express my architecture in such an abstract form whose logic-level simulations (without considering delays, area, routing, power and clock rate) will give a clear indication of win. FPGAs are simply not accurate tools for this: they are slow and big, and FPGA vendor's HDL compilation tool's results' performance measurements simply don't map well enough to actual chip's performance (which also depends on the synthesis and routing of the logic circuit). I need to know actual PDKs.

> General purpose processors and FPGAs are entirely different

Sure, but I specifically want to research the optimal intermediate point between classical CPU architectures and classical FPGA architectures.

> I just can't express my architecture in such an abstract form whose logic-level simulations (without considering delays, area, routing, power and clock rate) will give a clear indication of win.

Why not? There are plenty of open source RISC-V soft CPUs available for you to run on the same FPGA to benchmark against. If its the architecture which is special it doesn't matter if it competes against top of the line chips, just that it beats out everything comparable. You don't need to prove that your design will beat out a similarly designed chip on advanced silicon, just that your design implemented in the slow FPGA is better at something (not necessarily everything) than a CPU trying to emulate the same behavior. Having the PDKs won't help you much either, since on top of that it will take hundreds of thousands of dollars (minimum) in software costs and teams of people to help fine-tune and simulate such a large design. Doing this without the intention to eventually tape-out that design is a massive waste of resources.

I understand where you're coming from but the point of getting access to those PDKs isn't for rapid prototyping. The value proposition of your design must already be clear before beginning to design for a specific process. If you can't prove that your design has significant advantages that no chip in the next few years can possibly compete with, then there's just no point in attempting to design, synthesize, and simulate it on advanced nodes. That process is a significant investment in itself and if you're unsure enough about the potential benefits that you need to know exactly what it would look like in reality, then it's just too risky to spend the years it will take to get a working chip which may already be outclassed by the time your first chips come off of the line.

> Sure, but I specifically want to research the optimal intermediate point between classical CPU architectures and classical FPGA architectures.

That sounds cool, but this makes it sound like you're a really long way off from considering the specific characteristics of a given process node. Focus on designing an architecture which does something better than current designs can possibly do, such that the value of implementing it in a chip will be unquestionable.

Without PDK, how to prototype at all? My prototype will be so out of touch with actual reality of process parameters that it will have no value. Even if it outperforms soft CPUs, I will have to redesign from scratch at the point I will get actual PDK, since my business is not creating soft CPUs. Also how do you define "comparable" for a logic-level design? I don't get how such a metric stays useful when is tried to be used for measuring actual physical designs.

> You don't need to prove that your design will beat out a similarly designed chip on advanced silicon, just that your design implemented in the slow FPGA is better at something (not necessarily everything) than a CPU trying to emulate the same behavior.

No, I do. Since, again, my objective is creating actual chip, not a soft processor.

Fine-tuning will come only after it's clear that the design is good.

I just don't see a way to create such an abstract model which will have any utility for measurement.

And the advantages depend on actual implementation, which depends on process parameters, and if I try to make a design which is good regardless of actual parameters, this will be too conservative and I may not succeed.

You mean that it's an asynchronous design? Achronix makes FPGAs that can simulate that (they are spendy, but way less than actually fabbing a chip)

Edit: s/dabbing/fabbing/ lol

No, it's not asynchronous.

Then you're fine using commodity FPGAs, if it were me, id buy the biggest FPGAs altera currently makes, or just use their software simulator (it's great!)