I've thought about this a bit too after coming over from a digital logic background--it would be neat to have a language that let you specify multiple concurrent blocks that need to be run for each "clock" of the program and then just let the compiler interlace them as necessary for performance. In other words, just a high level verilog with a synthesis tool that generates high performance (possibly threaded) machine code. I do think though that most programmers would hate writing code in this way since it's a very foreign way of thinking for most SWEs, but it does have promise (especially in a post transistor scaling world).