It's not as bad as you think. From a high-level: Modern Synthesis tools turn your RTL code (which is coded in an HDL or Hardware Description Language) into gates, and then map them to a library of "Standard Cells". These foundry-specific cells are physical plans for an AND, OR, XOR, gates, flip-flops, etc. Once the code is mapped to these cells they are run through a Place&Route tool, which lays out all the mapped standard cells onto a plane, and then wires them together in 3D following a set of design rules from whatever foundry you are using. Finally after verifying the physical properties of the output design, you ship it to your foundry using a industry standard format called "GDS2" which is basically a series of 2D layers for turning into actual lithography masks. Doing this process (commonly called "RTL to GDS2") is non-trivial, but could be done to target a new foundry in <6 months. Now, Intel is known to use some custom layout methods rather than this Synthesized flow I've described, but that's pretty out of vogue and is a vestige of their early days.